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1 rev: c date:2/1/06 sp526 multi?ode serial transceiver ?copyright 2006 sipex corporation sp526 w an multi-mode serial transceiver description the sp526 is a monolithic device that sup- ports three (3) physical layer serial interface standards. the sp526 is fabricated using a low power bicmos process technology, and incorporates four (4) drivers and four (4) receivers can be configured via software for the selected interface modes at any time. the sp526 includes tri-state ability for the driver and receiver outputs through separate enable lines. a shutdown mode is also included through the mode select pins for power savings. when mated with the sp322 v.11/v.35 programmable transceiver, the sp526 provides the four (4) channels needed for handshaking/control lines such as cts, rts, etc. the two transceiver ics are an ideal solution for wan serial ports in networking equipment such as routers, dsu/csu's, and other access devices. low-cost programmable serial transceiver four (4) drivers and four (4)) receivers driver and receiver tri-state control software selectable protocol selection interface modes: ? rs-232 (v.28) ? rs-422 (v.11, x.21) ? eia-530 or rs-449 (v.10, v.11) designed to meet all net1/2 compliancy requirements high esd tolerance ? 15kv per human body model ? 15kv per iec1000-4-2 air discharge ? 8kv per iec1000-4-2 contact discharge t1 t2 t3 r1 r2 r3 t4 r4 sp526 1.0 f 1.0 f 1.0 f 1.0 f c2 1.0 f c1+ c1 c2+ t1in 8 ent1 12 t1outa t1outb t2outa t2outb t2in ent2 ent3 ent4 t3in t3outb t3outa t4out r1out r2out r3out r4out enr4 enr3 enr1 enr2 r1ina r2ina r3ina r4ina r3inb r4inb r2inb r1inb d0 d1 21 17 19 16 7 11 6 10 5 9 35 4 34 3 33 2 32 1 18 14 13 20 15 22 25 24 27 26 29 28 30 43 42 41 40 39 38 37 36 23 44 31 v dd v cc v cc +5v v ss gnd gnd gnd t4in sp526 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 enr4 enr3 enr2 enr1 t4in t3in t2in t1in ent4 ent3 ent2 ent1 d1 d0 v ss c2- c1- gnd c2+ v dd c1+ v cc r3out r4out v cc t4out t3outa t3outb t2outa t2outb t1outa t1outb gnd gnd r1ina r1inb r2ina r2inb r3ina r3inb r4ina r4inb r1out r2out now available in lead free packaging
2 rev: c date:2/1/06 sp526 multi?ode serial transceiver ?copyright 2006 sipex corporation - t a = +25 c and v cc = +4.75v to +5.25v unless otherwise noted. parameter min. typ. max. units conditions logic inputs v il 0.8 volts v ih 2.0 volts logic outputs v ol 0.4 volts i out = ?3.2ma v oh 2.4 volts i out = 1.0ma v.28 driver dc parameters outputs open circuit voltage 15 volts per figure 1 loaded voltage 5.0 15 volts per figure 2 short-circuit current 100 ma per figure 4 power-off impedance 300 ? per figure 5 ac parameters v cc = +5v for ac parameters outputs transition time 1.5 s per figure 6; +3v to -3v instantaneous slew rate 30 v/ s per figure 3 propagation delay t phl 0.5 1 5 s t plh 0.5 1 5 s max.transmission rate 120 230 kbps v.28 receiver dc parameters inputs input impedance 3 7 k ? per figure 7 open-circuit bias +2.0 volts per figure 8 high threshold 1.7 3.0 volts low threshold 0.8 1.2 volts ac parameters v cc = +5v for ac parameters propagation delay t phl 50 100 500 ns t plh 50 100 500 ns absolute maximum ratings these are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. v cc ............................................................................+7v input voltages: logic...............................-0.3v to (v cc +0.5v) drivers............................-0.3v to (v cc +0.5v) receivers........................................ 15.5v output voltages: logic................................-0.3v to (v cc +0.5v) drivers................................................ 15v receivers........................-0.3v to (v cc +0.5v) storage temperature..........................-65 ? c to +150 ? c power dissipation (derate 14.3mw/ ? c above 70 ? c)................ 1144mw storage considerations due to the relatively large package size of the 44-pin quad flat-pack, storage in a low humidity environment is preferred. large high density plastic packages are moisture sensitive and should be stored in dry vapor barrier bags. prior to usage, the parts should remain bagged and stored below 40 c and 60%rh. if the parts are removed from the bag, they should be used within 48 hours or stored in an environment at or below 20%rh. if the above conditions cannot be followed, the parts should be baked for four hours at 125 c in order remove moisture prior to soldering. sipex ships the 44-pin qfp in dry vapor barrier bags with a humidity indicator card and desiccant pack. the humidity indicator should be below 30%rh. electrical characteristics
3 rev: c date:2/1/06 sp526 multi?ode serial transceiver ?copyright 2006 sipex corporation t a = +25 c and v cc = +4.75v to +5.25v unless otherwise noted. parameter min. typ. max. units conditions v.28 receiver (continued) ac parameters (cont.) max.transmission rate 120 230 kbps v.10 driver dc parameters outputs open circuit voltage 4.0 6.0 volts per figure 9 test-terminated voltage 0.9v oc volts per figure 10 short-circuit current 150 ma per figure 11 power-off current 100 a per figure 12 ac parameters v cc = +5v for ac parameters outputs transition time 200 ns per figure 10; 10% to 90% propagation delay t phl 50 100 500 ns t plh 50 100 500 ns max.transmission rate 120 kbps v.11 driver dc parameters outputs open circuit voltage 5.0 volts per figure 14 test terminated voltage 2.0 volts per figure 15 0.5v oc 0.67v oc volts balance 0.4 volts per figure 15 offset +3.0 volts per figure 15 short-circuit current 150 ma per figure 16 power-off current 100 a per figure 17 ac parameters v cc = +5v for ac parameters outputs transition time 25 ns per figures 19 and 24; 10% to 90% propagation delay using r l = 100 ? and c l = 50pf; t phl 50 80 115 ns per figures 21 and 24 t plh 50 80 115 ns per figures 21 and 24 differential skew 20 40 ns per figures 21 and 24, t skew = | t dplh - t dphl | max.transmission rate 10 mbps v.11 receiver dc parameters inputs common mode range ? +7 volts sensitivity 0.38 volts electrical characteristics
4 rev: c date:2/1/06 sp526 multi?ode serial transceiver ?copyright 2006 sipex corporation - t a = +25 c and v cc = +4.75v to +5.25v unless otherwise noted. parameter min. typ. max. units conditions v.11 receiver (continued) dc parameters (cont.) input current ?.25 +3.25 ma per figure 18 and 20 input impedance 4 k ? ac parameters v cc = +5v for ac parameters propagation delay using r l = 100 ? and c l = 50pf; t phl 80 110 160 ns per figure 21 and 26 t plh 80 110 160 ns per figure 21 and 26 differential skew 20 ns per figure 21, t skew = | t plh - t phl | max. transmission rate 10 mbps power requirements v cc 4.75 5.00 5.25 volts i cc all i cc values are with v cc = +5v (v.28/rs-232) 35 45 ma f in = 120kbps; drivers active & loaded. (v.11/rs-422) 130 150 ma f in = 2.1mbps; drivers active & loaded. (eia-530/rs-449) 105 130 ma f in = 1.0mbps; drivers active & loaded. (shutdown) 4 a d0 = d1 = 0v, refer to table 1 environmental and mechanical operating temperature range 0 +70 c storage temperature range ?5 +150 c electrical characteristics
5 rev: c date:2/1/06 sp526 multi?ode serial transceiver ?copyright 2006 sipex corporation t a = +25 c and v cc = +5.0v unless otherwise noted. parameter min. typ. max. units conditions driver delay time between active mode and tri-state mode rs-232/v.28 drivers t pzl ; tri-state to output low 0.70 5.0 sc l = 100pf, fig. 22 & 28 ; s 1 closed t pzh ; tri-state to output high 0.40 2.0 sc l = 100pf, fig. 22 & 28 ; s 2 closed t plz ; output low to tri-state 0.20 2.0 sc l = 100pf, fig. 22 & 28 ; s 1 closed t phz ; output high to tri-state 0.40 2.0 sc l = 100pf, fig. 22 & 28 ; s 2 closed rs-423/v.10 drivers t pzl ; tri-state to output low 0.15 2.0 sc l = 100pf, fig. 22 & 28 ; s 1 closed t pzh ; tri-state to output high 0.20 2.0 sc l = 100pf, fig. 22 & 28 ; s 2 closed t plz ; output low to tri-state 0.20 2.0 sc l = 100pf, fig. 22 & 28 ; s 1 closed t phz ; output high to tri-state 0.15 2.0 sc l = 100pf, fig. 22 & 28 ; s 2 closed rs-422,/v.11 drivers t pzl ; tri-state to output low 2.80 10.0 sc l = 100pf, fig. 22 & 25; s 1 closed t pzh ; tri-state to output high 0.10 2.0 sc l = 100pf, fig. 22 & 25; s 2 closed t plz ; output low to tri-state 0.10 2.0 sc l = 15pf, fig. 22 & 25; s 1 closed t phz ; output high to tri-state 0.10 2.0 sc l = 15pf, fig. 22 & 25; s 2 closed receiver delay time between active mode and tri-state mode rs-232/v.28 receivers t pzl ; tri-state to output low 0.12 2.0 sc l = 100pf, fig. 23 & 27 ; s 1 closed t pzh ; tri-state to output high 0.10 2.0 sc l = 100pf, fig. 23 & 27 ; s 2 closed t plz ; output low to tri-state 0.10 2.0 sc l = 100pf, fig. 23 & 27 ; s 1 closed t phz ; output high to tri-state 0.10 2.0 sc l = 100pf, fig. 23 & 27 ; s 2 closed rs-422/v.11receivers t pzl ; tri-state to output low 0.10 2.0 sc l = 100pf, fig. 23 & 27; s 1 closed t pzh ; tri-state to output high 0.10 2.0 sc l = 100pf, fig. 23 & 27; s 2 closed t plz ; output low to tri-state 0.10 2.0 sc l = 15pf, fig. 23 & 27; s 1 closed t phz ; output high to tri-state 0.10 2.0 sc l = 15pf, fig. 23 & 27; s 2 closed other ac characteristics
6 rev: c date:2/1/06 sp526 multi?ode serial transceiver ?copyright 2006 sipex corporation - pinout pin description pin 1 ?enr4 ?enables receiver 4; active high; ttl input. pin 2 ?enr3 ?enables receiver 3; active high; ttl input. pin 3 ?enr2 ?enables receiver 2; active high; ttl input. pin 4 ?enr1 ?enables receiver 1; active high; ttl input. pin 5 ?t4in ?ttl input; transmit data source for dra4 and drb4 outputs. pin 6 ?t3in ?ttl input; transmit data source for dra3 and drb3 outputs. pin 7 ?t2in ?ttl input; transmit data source for dra2 and drb2 outputs. pin 8 ?t1in ?ttl input; transmit data source for dra1 and drb1 outputs. pins 9 ?ent4 ?enables driver 4, active low; ttl input. pins 10 ?ent3 ?enables driver 3, active low; ttl input. pins 11 ?ent2 ?enables driver 2, active low; ttl input. pins 12 ?ent1 ?enables driver 1, active low; ttl input. pins 13 ?d1 ?transmitter and receiver decode register; configures transmitter and receiver modes; ttl inputs. sp526 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 enr4 enr3 enr2 enr1 t4in t3in t2in t1in ent4 ent3 ent2 ent1 d1 d0 v ss c2- c1- gnd c2+ v dd c1+ v cc r3out r4out v cc t4out t3outa t3outb t2outa t2outb t1outa t1outb gnd gnd r1ina r1inb r2ina r2inb r3ina r3inb r4ina r4inb r1out r2out
7 rev: c date:2/1/06 sp526 multi?ode serial transceiver ?copyright 2006 sipex corporation pins 14 ?d0 ?transmitter and receiver decode register; configures transmitter and re- ceiver modes; ttl inputs. pin 15 ?v ss ? 10v charge pump capacitor ?connects from ground to v ss . suggested capacitor size is 1.0 f, 16v. pin 16 ?c 2 ?charge pump capacitor connects from c 2 + to c 2 . suggested capacitor size is 1.0 f, 16v. pin 17 ?c 1 ?charge pump capacitor connects from c 1 + to c 1 . suggested capacitor size is 1.0 f, 16v. pin 18 ?gnd ?ground. pin 19 ?c 2 + ?charge pump capacitor connects from c 2 + to c 2 . suggested capacitor size is 1.0 f, 16v. pin 20 ?v dd ? + 10v charge pump capacitor ?connects from v dd to v cc . suggested capacitor size is 1.0 f, 16v. pin 21 ?c 1 + ?charge pump capacitor connects from c 1 + to c 1 . suggested capacitor size is 1.0 f, 16v. pin 22 ?v cc ?+5v input. pin 23 ?gnd ?ground. pin 24 ?t1outb ?analog out ?send data, non-inverted; sourced from tin1. pin 25 ?t1outa ?analog out ?send data, inverted; sourced from tin1. pin 26 ?t2outb ?analog out ?send data, non-inverted; sourced from tin2. pin 27 ?t2outa ?analog out ?send data, inverted; sourced from tin2. pin 28 ?t3outb ?analog out ?send data, non-inverted; sourced from tin3. pin 29 ?t3outa ?analog out ?send data, inverted; sourced from tin3. pin 30 ?t4out ?analog out ?send data, inverted; sourced from tin4. pin 31 ?v cc ?+5v input. pin 32 r4out ?ttl output; sourced from rina4 and rinb4 inputs. pin 33 r3out ?ttl output; sourced from rina3 and rinb3 inputs. pin 34 r2out ?ttl output; sourced from rina2 and rinb2 inputs. pin 35 r1out ?ttl output; sourced from rina1 and rinb1 inputs. pin 36 r4inb ?non-inverted analog input to receiver 4. pin 37 ?r4ina ?inverted analog input to receiver 4. pin 38 r3inb ?non-inverted analog input to receiver 3. pin 39?r3ina ?inverted analog input to receiver 3. pin 40 r2inb ?non-inverted analog input to receiver 2. pin 41 ?r2ina ?inverted analog input to receiver 2. pin 42 r1inb ?non-inverted analog input to receiver 1. pin 43 ?r1ina ?inverted analog input to receiver 1. pin 44 ?gnd ?ground.
8 rev: c date:2/1/06 sp526 multi?ode serial transceiver ?copyright 2006 sipex corporation - a v oc c a v t c 3k ? a v t c 7k ? oscilloscope scope used for slew rate measurement. a i sc c a c v cc = 0v 2v i x a c 3k ? 2500pf oscilloscope figure 1. v.28 driver output open circuit voltage figure 2. v.28 driver output loaded voltage figure 3. v.28 driver output slew rate figure 4. v.28 driver output short-circuit current figure 6. driver output rise/fall times figure 5. v.28 driver output power-off impedance test circuits
9 rev: c date:2/1/06 sp526 multi?ode serial transceiver ?copyright 2006 sipex corporation figure 7. v.28 receiver input impedance a c i ia 15v a c v oc figure 8. v.28 receiver input open circuit bias a v oc 3.9k ? c a v t 450 ? c a c 0.25v v cc = 0v i x a i sc c figure 9. v.10 driver output open-circuit voltage figure 10. v.10 driver output test terminated voltage figure 12. v.10 driver output power-off current figure 11. v.10 driver output short-circuit current
10 rev: c date:2/1/06 sp526 multi?ode serial transceiver ?copyright 2006 sipex corporation - figure 13. v.10 driver output transition time a 450 ? c oscilloscope figure 14. v.11 driver output open-circuit voltage a b v oc 3.9k ? v oca v ocb c a b v t 50 ? v os c 50 ? a b c i sa i sb figure 15. v.11 driver output test terminated voltage figure 16. v.11 driver output short-circuit current
11 rev c date:2/1/06 sp526 multi?ode serial transceiver ?copyright 2006 sipex corporation a b c i xa 0.25v a b c i xb 0.25v v cc = 0v v cc = 0v a b c i ia 10v c i ib 10v a b +3.25ma ?.25ma +10v +3v ?v ?0v maximum input current ve r s us vo l t a ge v.1 1 re ce iv er figure 17. v.11 driver output power-off current figure 18. v.11 receiver input current figure 19. v.11 driver output rise/fall time figure 20. v.11 receiver input iv graph a b 50 ? c 50 ? 50 ? v e oscilloscope
12 rev: c date:2/1/06 sp526 multi?ode serial transceiver ?copyright 2006 sipex corporation - figure 22. driver timing test load circuit figure 23. receiver timing test load circuit 500 ? c l output under tes t s 1 s 2 v cc 1k ? 1k ? c rl receiver ou tpu t s 1 s 2 test point v cc figure 24. driver propagation delays +3v 0v driver input b a driver output v o + differential output v a ?v b 0v v o 1.5v 1.5v t plh t r t f f = 1mhz; t r 10ns; t f 10ns v o 1/2v o 1/2v o t phl t skew = |t dplh - t dphl | t dphl t dplh figure 25. v.11 driver enable and disable times +3v 0v de c x or t x_ e nable 5v v ol a, b 0v 1.5v 1.5v t zl t zh f=1mhz; t r < 10ns; t f <10ns v oh a, b 2.3v 2.3v t lz t hz 0.5 v 0.5 v output norm a lly low output no rma lly hi gh figure 21. driver/receiver timing test circuit c l1 1 5pf ro a b a b di c l2 r l d x or t x _enable
13 rev: c date:2/1/06 sp526 multi?ode serial transceiver ?copyright 2006 sipex corporation figure 27. receiver enable and disable times +3v 0v dec x 5v 0v 1.5v 1.5v t zl t zh f = 1mhz; t r 10ns; t f 10ns receiver out 50% 50% t lz t hz 0.5v 0.5v output normally low output normally high v il v ih receiver out d0 or d1 figure 26. receiver propagation delays v oh v ol receiver out 50% t plh f = 1mhz; t r 10ns; t f 10ns output v od2 + v od2 a ?b 0v 0v t phl input 50% t skew = |t phl - t plh | figure 28. v.28 (rs-232) and v.10 driver enable and disable times +3v 0v d x or ent x 1.5v 1.5v t zl f = 60khz; t r < 10ns; t f < 10ns t out t lz output low 0v +3v 0v v oh(min) 1.5v 1.5v t zh f = 60khz; t r < 10ns; t f < 10ns t out t hz output high 0v v ol(min) d x or ent x 0.5v 0.5v 0.5v 0.5v
14 rev: c date:2/1/06 sp526 multi?ode serial transceiver ?copyright 2006 sipex corporation - t1 t2 t3 r1 r2 r3 t4 r4 sp526 1.0 f 1.0 f 1.0 f 1.0 f c2 1.0 f c1+ c1 c2+ t1in 8 ent1 12 t1outa t1outb t2outa t2outb t2in ent2 ent3 ent4 t3in t3outb t3outa t4out r1out r2out r3out r4out enr4 enr3 enr1 enr2 r1ina r2ina r3ina r4ina r3inb r4inb r2inb r1inb d0 d1 21 17 19 16 7 11 6 10 5 9 35 4 34 3 33 2 32 1 18 14 13 20 15 22 25 24 27 26 29 28 30 43 42 41 40 39 38 37 36 23 44 31 v dd v cc v cc +5v v ss gnd gnd gnd t4in figure 29. typical operating circuit for the sp526
15 rev: c date:2/1/06 sp526 multiCmode serial transceiver ? copyright 2006 sipex corporation theory of operation the sp526 device is made up of 1) the drivers, 2) the receivers, and 3) a charge pump. drivers the sp526 has four enhanced independent drivers. control for the mode selection is done via a twoCbit control word into dp0 and dp1. the drivers are prearranged such that for each mode of operation, the relative position and functionality of the drivers are set up to accommodate the selected interface mode. as the mode of the drivers is changed, the electrical characteristics will change to support the required signal levels. the mode of each driver in the different interface modes that can be selected is shown in table 1. there are four basic types of driver circuits rs-232 (v.28), rs-423 (v.10), rs-422 (v.11), and rs-485. the rs-232 (v.28) drivers output singleCended signals with a minimum of ? 5v (with 3k ? & 2500pf loading), and can operate to at least 120kbps. since the sp526 uses a charge pump to generate the rs-232 output rails, the driver outputs will never exceed ? 10v. the rs-423 (v.10) drivers are also singleC ended signals which produce open circuit v ol and v oh measurements of ? 4.0v to ? 6.0v. when terminated with a 450 ? load to ground, the driver output will not deviate more than 10% of the open circuit value. this is in compliance features the sp526 contains highly integrated serial transceivers that offer programmability between interface modes through software control. the sp526 offers the hardware interface modes for rs-232 (v.28), rs-423 (v.10), rs-422 (v.11), and rs-485. the interface mode selection is done via two control pins. the sp526 has four drivers, four receivers, and an on-board charge pump that is ideally suited for low-cost wide area network connectivity and other multi-protocol applications. based on our multi-mode sp500 family, sipex has allocated specific transceiver cells, or "building blocks," from this product series and created the sp526 . sipex's "building blocks" concept allows these small transceiver cells to be packaged to offer a simple low-cost solution to networking applications that need only 4 interface modes. for example, an 8-channel applications requiring eight serial transceivers can be achieved implementing two sp526 devices. the sp526 can be implemented in series with other devices in our sp500 family. a 9-channel network application can be achieved implementing the sp505 which contains seven transceivers in conjunction with the sp526 . 1 d 0 d s r e v i r d s r e v i e c e r 1 t 2 t 3 t 4 t 1 r 2 r 3 r 4 r 0 0 e d o m e t a t s - i r t n i s t u p t u o x r d n a x t - n w o d t u h s 0 1 1 1 . v 1 1 . v 1 1 . v 0 1 . v 1 1 . v 1 1 . v 1 1 . v 1 1 . v 1 0 1 1 . v 1 1 . v 0 1 . v 0 1 . v 1 1 . v 1 1 . v 1 1 . v 1 1 . v 1 1 8 2 . v 8 2 . v 8 2 . v 8 2 . v 8 2 . v 8 2 . v 8 2 . v 8 2 . v table 1. sp526 driver and receiver mode selection with the control lines d1 and d0 d1 d0 drivers receivers t1 t2 t3 t4 w r1 r2 r3 r4 0 0 shutdown - tx and rx outputs in tri-state mode 0 1 v.11 v.11 v.11 v.10 v.11 v.11 v.11 v.11 1 0 v.11 v.11 v.10 v.10 v.11 v.11 v.11 v.11 1 1 v.28 v.28 v.28 v.28 v.28 v.28 v.28 v.28 table 1. sp526 driver and receiver mode selection with the control lines d1 and d0 t1a t1b t2a t2b t3a t3b t4 r1a r1b r2a r2b r3a r3b r4a r4b 0 0 0 1 v.11 v.11 v.11 v.11 v.11 v.11 v.10 v.11 v.11 v.11 v.11 v.11 v.11 v.11 v.11 1 0 v.11 v.11 v.11 v.11 v.10 v.10 v.10 v.11 v.11 v.11 v.11 v.11 v.11 v.11 v.11 1 1 v.28 x v.28 x v.28 x v.28 v.28 x v.28 x v.28 x v.28 x r1a hi g h z d1 d0 drivers receivers
16 rev: c date:2/1/06 sp526 multi?ode serial transceiver ?copyright 2006 sipex corporation - of the itu v.10 specification. the rs-423 drivers are used in rs-449, eia-530, eia-530a and v.36 modes as category ii signals from each of their corresponding specifications. the third and fourth type of drivers are rs-422 (v.11)/rs-485 type differential drivers. due to the nature of differential signaling, the drivers are more immune to noise as opposed to single- ended transmission methods. the advantage is evident over high speeds and long transmission lines. the strength of the driver outputs can produce differential signals that can maintain rs-485, 1.5v differential output levels with a worst case load of 54 ? . the signal levels and drive capability of these drivers allow the driv- ers to also support rs-422 (v.11) requirements of 2v differential output levels with 100 ? loads. the driver is designed to operate over a common mode range of +7v to -7v which follows the v.11 specification. the rs-422 drivers are used in rs-449, eia-530, eia-530a and v.36 modes as category i signals which are used for clock and data. all of the differential drivers can operate to at least 10mbps. the drivers also have separate enable pins which simplifies half-duplex configurations for some applications and also provides simpler dte/ dce flexibility with one integrated circuit. the enable pins will tri-state the drivers when the ent1, ent2, ent3, and ent4 pins are at a logic high ("1"). during tri-stated conditions, the driver outputs will be at a high impedance state. the driver inputs are both ttl or cmos com- patible. each driver input should have a pull- down or pull-up resistor so that the output will be at a defined state. unused driver inputs should have pull-up resistors to +5v connected so that the output is at a logic low ("0"). unused driver inputs should not be left floating. for differential drivers, the non-inverting out- put will be at a logic high ("1"). the typical pull-up resistor value should be 400k ? . receivers the sp526 has four independent receivers which can be programmed for the different interface modes. control for the mode selection is done via a two?it control word that is the same as the driver control word. therefore, if the modes for the drivers and receivers are supposed to be identical in the application, the control lines can be tied together. like the drivers, the receivers are prearranged for the specific requirements of the synchronous serial interface. as the operating mode of the receivers is changed, the electrical characteris- tics will change to support the required serial interface protocols of the receivers. table 1 shows the mode of each receiver in the different interface modes that can be selected. there are two basic types of receiver circuits rs-232 (v.28) and rs-422 (v.11). the rs-232 (v.28) receiver is single?nded and accepts rs-232 signals from the rs-232 driver. the rs-232 receiver has an operating voltage range of 15v and can receive signals downs to 3v. the input sensitivity complies with rs- 232 and v.28 at 3v. the input impedance is 3k ? to 7k ? in accordance to rs-232 and v.28. the receiver output produces a ttl/cmos signal with a +2.4v minimum for a logic "1" and a +0.8v maximum for a logic "0". rs-232(v.28) receivers can be used in rs-232 mode for data, clock or control signals. they are also used in v.35 mode for control line signals: cts, dsr, ll, and rl. the rs-232 receivers can operate to at least 120kbps.
17 rev: c date:2/1/06 sp526 multi?ode serial transceiver ?copyright 2006 sipex corporation the third type of receiver is a differential which supports rs-422/v.11 signals. this receiver has a typical input impedance of 10k ? and a differential threshold of 0.3v, which complies with the rs-422/v.11 specifications. since the characteristics of the rs-422 (v.11) receivers are actually subsets of rs-485, the rs-422/ v.11 receivers can accept rs-485 signals. however, these receivers cannot support 32 transceivers on the signal bus due to the lower input impedance as specified in the rs-485 specifications. v.11 receivers are used in rs-422, rs-449, eia-530, eia-530a and v.36 as category i signals for receiving clock, data, and some control line signals not covered by category ii v.10 circuits. the differential receivers can receive signals up to at least 10mbps. all four receivers include an enable line for tri-state of the receiver output allowing convenient half-duplex configurations. when the enable lines are at a logic low ("0") active, the receiver outputs are high impedance and will be at approximately 10k ? during tri-state. all receivers include a fail-safe feature that outputs a logic high when the receiver inputs are open. for single-ended rs-232 receivers, there are internal 5k ? pull-down resistors on the inputs which produces a logic high ("1") at the receiver outputs. the single-ended rs-423 receivers produce a logic low ("0") on the output when the inputs are open. this is due to a pull-up device connected to the input. the differential receivers have the same internal pull-up device on the non-inverting input which produces a logic high ("1") at the receiver output. charge pump the charge pump is a sipex ?atented design (u.s. 5,306,954) and uses a unique approach compared to older less?fficient designs. the charge pump still requires four external capaci- tors, but uses a four?hase voltage shifting technique to attain symmetrical 10v power supplies. there is a free?unning oscillator that controls the four phases of the voltage shifting. a description of each phase follows. phase 1 ?v ss charge storage ?uring this phase of the clock cycle, the positive side of capacitors c 1 and c 2 are initially charged to +5v. c l + is then switched to ground and the charge in c 1 is transferred to c 2 . since c 2 + is connected to +5v, the voltage potential across capacitor c 2 is now 10v. phase 2 ?v ss transfer ?phase two of the clock connects the negative terminal of c 2 to the v ss storage capacitor and the positive terminal of c 2 to ground, and transfers the generated ?0v to c 3 . simultaneously, the positive side of capacitor c 1 is switched to +5v and the negative side is connected to ground. phase 3 ?v dd charge storage ?the third phase of the clock is identical to the first phase ?the charge transferred in c 1 produces ?v in the negative terminal of c 1 , which is applied to the negative side of capacitor c 2 . since c 2 + is at +5v, the voltage potential across c 2 is l0v. c 1 + - -5v v cc = +5v +5v c 2 -5v c 4 c 3 + - + - - + v dd storage capacitor v ss storage capacitor figure 30. charge pump ?phase 1
18 rev: c date:2/1/06 sp526 multi?ode serial transceiver ?copyright 2006 sipex corporation - figure 31. charge pump ?phase 2 c 1 + - v cc = +5v c 2 -10v c 4 c 3 + - + - - + v dd storage capacitor v ss storage capacitor figure 32. charge pump waveforms +10v a) c 2 + gnd gnd b) c 2 ?0v figure 33. charge pump ?phase 3 c 1 + - -5v v cc = +5v +5v c 2 -5v c 4 c 3 + - + - - + v dd storage capacitor v ss storage capacitor figure 34. charge pump ?phase 4 c 1 + - v cc = +5v +10v c 2 c 4 c 3 + - + - - + v dd storage capacitor v ss storage capacitor
19 rev: c date:2/1/06 sp526 multi?ode serial transceiver ?copyright 2006 sipex corporation phase 4 ?v dd transfer ?the fourth phase of the clock connects the negative terminal of c 2 to ground, and transfers the generated l0v across c 2 to c 4 , the v dd storage capacitor. again, simultaneously with this, the positive side of capacitor c 1 is switched to +5v and the negative side is con- nected to ground, and the cycle begins again. since both v + and v are separately generated from v cc ; in a no?oad condition v + and v will be symmetrical. older charge pump approaches that generate v from v + will show a decrease in the magnitude of v compared to v + due to the inherent inefficiencies in the design. the clock rate for the charge pump typically operates at 15khz. the external capacitors can be as low as 1.0 f with a 16v breakdown voltage rating. esd tolerance the sp526 device incorporates ruggedized esd cells on all driver output and receiver input pins. the esd structure is improved over our previous family for more rugged applications and environments sensitive to electro-static discharges and associated transients. the improved esd tolerance is at least 15kv without damage nor latch-up. there are different methods of esd testing applied: a) mil-std-883, method 3015.7 b) iec1000-4-2 air-discharge c) iec1000-4-2 direct contact the human body model has been the generally accepted esd testing method for semiconductors. this method is also specified in mil-std-883, method 3015.7 for esd testing. the premise of this esd test is to simulate the human body? potential to store electro-static energy and discharge it to an integrated circuit. the simulation is performed by using a test model as shown in figure 35. this method will test the ic? capability to withstand an esd transient during normal handling such as in manufacturing areas where the ics tend to be handled frequently. the iec-1000-4-2, formerly iec801-2, is generally used for testing esd on equipment and systems. for system manufacturers, they must guarantee a certain amount of esd protection since the system itself is exposed to the outside environment and human presence. the premise with iec1000-4-2 is that the system is required to withstand an amount of static electricity when esd is applied to points and surfaces of the equipment that are accessible to personnel during normal usage. the transceiver ic receives most r c sw dc power source c s r s sw2 device under t est figure 35. esd test circuit for human body model
20 rev: c date:2/1/06 sp526 multi?ode serial transceiver ?copyright 2006 sipex corporation - 30a 15a 0a t=0ns t=30ns t figure 37. esd test waveform for iec1000-4-2 of the esd current when the esd source is applied to the connector pins. the test circuit for iec1000-4-2 is shown on figure 36 . there are two methods within iec1000-4-2, the air discharge method and the contact discharge method. with the air discharge method, an esd voltage is applied to the equipment under test (eut) through air. this simulates an electrically charged person ready to connect a cable onto the rear of the system only to find an unpleasant zap just before the person touches the back panel. the high energy potential on the person discharges through an arcing path to the rear panel of the system before he or she even touches the system. this energy, whether discharged directly or through air, is predominantly a function of the discharge current rather than the discharge voltage. variables with an air discharge such as approach speed of the object carrying the esd table 2. transceiver esd tolerance levels device pin human body iec1000-4-2 tested model air discharge direct contact level driver outputs 15kv 15kv 8kv 4 receiver inputs 15kv 15kv 8kv 4 r c c s r s r v sw1 sw2 contact-discharge module device under t est dc power source rs and rv add up to 330 ? for iec1000-4-2 figure 36 . esd test circuit for iec1000-4-2
21 rev: c date:2/1/06 sp526 multi?ode serial transceiver ?copyright 2006 sipex corporation potential to the system and humidity will tend to change the discharge current. for example, the rise time of the discharge current varies with the approach speed. the contact discharge method applies the esd current directly to the eut. this method was devised to reduce the unpredictability of the esd arc. the discharge current rise time is constant since the energy is directly transferred without the air-gap arc. in situations such as hand held systems, the esd charge can be directly discharged to the equipment from a person already holding the equipment. the current is transferred on to the keypad or the serial port of the equipment directly and then travels through the pcb and finally to the ic. the circuit models in figures 35 and 36 represent the typical esd testing circuits used for all three methods. the c s is initially charged with the dc power supply when the first switch (sw1) is on. now that the capacitor is charged, the second switch (sw2) is on while sw1 switches off. the voltage stored in the capacitor is then applied through r s , the current limiting resistor, onto the device under test (dut). in esd tests, the sw2 switch is pulsed so that the device under test receives a duration of voltage. for the human body model, the current limiting resistor (r s ) and the source capacitor (c s ) are 1.5k ? an 100pf, respectively. for iec-1000-4- 2, the current limiting resistor (r s ) and the source capacitor (c s ) are 330 ? an 150pf, respectively. the higher c s value and lower r s value in the iec1000-4-2 model are more stringent than the human body model. the larger storage capacitor injects a higher voltage to the test point when sw2 is switched on. the lower current limiting resistor increases the current charge onto the test point. net1/net2 european compliancy as with all of sipex's previous multi-protocol serial transceiver ics, the drivers and receivers have been designed to meet all the requirements to net1/net2. the sp526 is also tested and adheres to all the net1/2 physical layer testing and the itu series v specifications. please note that although the sp526 , as with its predecessors, adheres to net1/2 testing, any complex or unusual configuration should be double-checked to ensure net compliance. consult the factory for details.
22 rev: c date:2/1/06 sp526 multi?ode serial transceiver ?copyright 2006 sipex corporation - package:44 pin lqfp 44 pin lqfp l 11 - 13 0 min 11 - 13 0 ? dimensions minimum/maximum (mm) symbol a a1 a2 b d d1 e e e1 n 44?pin lqfp jedec ms-026 (bcb) variation min nom max 1.60 0.05 0.15 1.35 1.40 1.45 0.30 0.37 0.50 12.00 bsc 10.00 bsc 0.80 bsc 12.00 bsc 10.00 bsc 44 c l1 common dimentions symbl min nom max c 0.11 23.00 l 0.73 0.88 1.03 l1 0.25 basic b e a2 0.2 rad. max. 0.08 rad. min. seating plane a1 aa e 1 d 1 d c l c l -d- pin 1 e
23 rev: c date:2/1/06 sp526 multi?ode serial transceiver ?copyright 2006 sipex corporation ordering information part number temperature range package types sp526cf------------------------------------------------------------- 0 c to +70 c------------------------------------------------------------------- 44?in jedec lqfp corporation solved by sipex sipex corporation reserves the right to make changes to any products described herein. sipex does not assume any liability aris ing out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor t he rights of others. please consult the factory for pricing and availability on a tape-on-reel option. sipex corporation headquarters and sales office 233 south hillview drive milpitas, ca 95035 tel: (408) 934-7500 fax: (408) 935-7600 sales office 22 linnell circle billerica, ma 01821 tel: (978) 667-8700 fax: (978) 670-9001 e-mail: sales@sipex.com date revision description 1/27/04 a implemented tracking revision. 7/7/04 b available in lqfp package. 2/1/06 c added table describing pin function in different modes. revision history available in lead free packaging. to order add ?l?suffix to part number. example: sp526cf = standard; sp526cf-l = lead free
date changes implemented input source 29-nov-05 changing links and metatags for more suitable search en g ine results. brad hudon 06-dec-05 ordering information can't have dots, must have dashes. mark levi 11-jan-06 added "solved by sipex tm" @ end kevin o'malle y 02-feb-06 added modes table. mike delurio pod this information is not to be g iven out to customers.

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